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VHDL  
 
 

VHDL is a versatile and powerful hardware description language which is useful for modeling electronic systems at various levels of design abstraction. VHDL includes facilities for describing logical structure and function of digital systems at a number of levels of abstraction, from system level down to the gate level. VDHL is used in electronic design automation to describe digital and mixed-signal systems such as field-programmable gate arrays and integrated circuits. VHDL is frequently used for two different goals simulation of electronic designs and synthesis of such designs.

VHDL is commonly used to write text models that describe a logic circuit, Such a model is processed by a synthesis program, only if it is part of the logic design. VHDL has input and output capabilities, So it has construct to handle the parallelism inherent in hardware designs. VHDL allows designs to be described using any methodology - top down, bottom up or middle out. VHDL can be used to describe hardware at the gate level or in a more abstract way. And successful high level design requires a language, a tool set and a suitable methodology.


Some Basic VHDL Constructs are

1. Data types

2. Objects

3. Sequential and concurrent statements

4. Packages and libraries

5. Attributes

6. Predefined operators

 

Courses and Eligibility

1. Student must pass higher secondary education or 10+2 with any subjects to get     admission into bachelor’s degree program.

2. BE in Electrical or Electronics and Communication.

3. BE in Computer or Information Science.

 

Employment

Graduates are employed in all IT companies, Public and Private Organizations, and Manufacturing industries, product companies, design service companies and electronic design automation companies.

 
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